Makefiles

When developing applications that use a large number of subroutines spread across many files, it can be tedious to have to recompile and relink various things when the sources change. For this, the use of a Makefile, and a companion program make, can be very convenient.

For example, suppose we have a file subs.c containing a collection of subroutines, and a file prog.c containing a main routine that uses them. Construct a file Makefile containing the following (in this, the presence of tab characters are significant):

CC = gcc
HOME = /usr/home/me
INCDIR = $(HOME)/include
LIBDIR = $(HOME)/lib
INCFLAG = -I$(INCDIR)
LIBFLAG = -L$(LIBDIR) -lm

all: prog

prog: prog.c subs.o
        $(CC) -o prog prog.c subs.o $(INCFLAG) $(LIBFLAG)

subs.o: subs.c
        $(CC) -c subs.c $(INCFLAG)

clean:
        rm -f subs.o prog

The program can then be built as

   make

which will carry out the commands in the Makefile. One of the advanatages to using this is that if any of the source files are changed, simply invoking make again will figure out what components need rebuilding.

Entire books can (and have) been written on writing and using Makefiles; the above example only scratches the surface. What is illustrated in the above example is the use of

• variables or macros, by which something can be defined as VARNAME = some command, and then invoked later on as $(VARNAME);
• it target: dependency: this specifies, to the left of the colon, a target, with what appears to the right a dependency, which should be satisfied to build the target. The command (or series of commands) on subsequent lines is what defines the target (here, tab characters are significant). Specific targets can be built as make target_name; the first target specified (all in the above example) is what will be used as a default when make (without any target) is specified.